• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
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  • 优先权
    • 专利摘要:
    A fractional divider divides the input frequency of the first signal Fi into a non-integer rational number, which is greater than 1 and 1 if recorded as a vulgar fraction. Can only be written as a denominator which is not equal to The apparatus comprises a plurality of series connected delay elements (a, b, c, ..., R). Each of the delay elements a, b, c, ..., R adds a predetermined delay to the signal of the preceding delay elements a, b, ..., R-1. The first signal Fi is applied to the first delay element a. The delay added continuously for each delay element is equal to the period of the first signal Fi divided by the denominator of the rational fraction. The counter 2 counts the pulses of the first signal Fi, which counts by increasing the denominator of the rational number and calculating it modulo with the numerator of the rational number. The decoder circuit 6 decodes the counting score of the counter, which appears continuously at the outputs 6a, ..., 6e of the decoder circuit 6 according to the counting score and the algorithm. The coupling circuits 6, 7, 8, 10, 11, 12, 13 decode the output signals of the delay elements a, b, ..., R determined by the algorithm to obtain the second signal Fo. Means 7, 8, 10, 11, 12, 13 for coupling with the output signal of the circuit 6.
    公开号:KR20020019541A
    申请号:KR1020027000713
    申请日:2001-04-24
    公开日:2002-03-12
    发明作者:버린든요젭제이에이엠
    申请人:롤페스 요하네스 게라투스 알베르투스；코닌클리즈케 필립스 일렉트로닉스 엔.브이.；
    IPC主号:
    专利说明:

    Signal generator and phase locked loop circuit {FRACTIONAL N-DIVIDER, AND FREQUENCY SYNTHESIZER PROVIDED WITH A FRACTIONAL N-DIVIDER}
    [2] Such devices are widely used in frequency synthesizers with phase locked loop (PLL) circuits, known and hereafter referred to as PPL frequency synthesizers.
    [3] The frequency step size of the output signal of the PPL frequency synthesizer is equal to the input frequency. Frequency resolution increases with smaller step size. If very high frequency resolution is required, a low input frequency should be used. In practice, low input frequencies usually involve a small bandwidth of the PPL, thus preventing undesirable effects such as oscillation and the like. However, the small bandwidth of the PLL allows for slow tuning, ie long tuning periods, insufficient protection of phase noise of voltage-controlled oscillators, sensitivity to hum and noise. And undesirable jitter of clock signal. In addition, such circuits are difficult to implement in integrated circuits.
    [4] The problems outlined above are a number of delays connected in series to further delay the first signal per delay element each time by a period equal to the period of the first signal divided by the denominator of the vulgar fraction. The present invention is characterized by a combination circuit comprising means for providing a first signal to a first delay element of a delay element and a counter for counting pulses of the first signal. This counting can be prevented to a considerable extent by counting takes place modulo the numerator of the rational number and in steps of the denominator of the rational number, as a result, a counter score is generated and the combining circuit is based on a counter score based on an algorithm determined by the rational number. A decoder that decodes the word, wherein the decoded counter score described above is represented as an output signal at one output of the decoder circuit, each time determined by a counter score and an algorithm, and the combining circuit is configured to obtain a second signal. Means for combining the output signal of the delay element determined by the algorithm with the output signal of the decoder circuit.
    [5] Summary of the Invention
    [6] Thus, it is possible to achieve a divisional ratio having a rational number which is non-integer. The jitter of the divider circuit depends only on the intrinsic jitter of the system when the number of delay elements is equal to the denominator of the rational number.
    [7] If the number of delay elements is smaller than the denominator of the rational number, the jitter imposed on the resolution becomes equal to the duration of the first signal divided by the number of delay elements.
    [8] The device according to the invention has greater bandwidth, short tuning time, less noise (low jitter, less spectral contamination) and higher resolution, is inexpensive and can be easily integrated into an integrated circuit.
    [9] A preferred embodiment of the device according to the invention is characterized in that the delay element is connected as a delay locked loop circuit.
    [10] A phase locked loop circuit comprising a feedback loop is characterized in that an apparatus as described above is included in the feedback loop.
    [11] A known solution to avoid the problem of small bandwidth is to quickly switch between two dividers between the output of the PLL circuit and the input of the PLL circuit. This is called dither. The division then takes place, for example, by two large numbers which are in close proximity together, for example 4 and 5. This is equivalent to dividing by an average of 4.5. However, the second frequency can therefore be corrected on average, but need not be done at the same time, ie at each moment and every moment. Dividing into two numbers with a difference less than one is also possible in a simple manner in this kind of circuit. The apparatus according to the invention as described above makes this possible.
    [12] A phase locked loop circuit according to the invention comprising a dither possibility feedback loop is characterized in that the device as described above is included in the feedback loop.
    [1] The present invention relates to an apparatus for generating a second signal having a frequency equal to the frequency of a first signal divided by a non-integer rational number, wherein the rational number is greater than one and a vulgar fraction. If written as, it can only be written as a denominator that is not equal to one.
    [13] The invention will be described in detail below with reference to the accompanying drawings.
    [14] 1 is a schematic diagram of a phase locked loop frequency synthesizer,
    [15] 2 is a graph showing an example of 13/6 division of the signal Fi,
    [16] FIG. 3 is a table illustrating the relationship between periods of Fi, counter scores, 1-0 and 0-1 changes, and the period between successive 0-1 changes,
    [17] 4 is a schematic diagram of a circuit in which the method according to FIGS. 2 and 3 can be implemented;
    [18] 5 is a schematic representation of a first application of a fractional N-divider,
    [19] 6 is a schematic diagram of a second application of a fractional N-divider.
    [20] 1 shows a frequency synthesizer circuit using a phase locked loop circuit in its widest form. Since Fo = (P / (Q1 * Q2)) * Fr, the circuit shown can implement a certain rational ratio between Fo and Fr with integers P, Q1 and Q2.
    [21] The frequency step size of the output signal of the phase locked loop synthesizer of FIG. 1 is equal to Fr / Q1. If a high frequency resolution is required, the result is that Fr / Q1 should be small. This also means that the bandwidth of the loop formed by the phase locked loop circuit PLL and divider P must be small. However, the smaller bandwidth of the loop will generally result in longer tuning time of the circuit as the bandwidth is smaller, insufficient protection of phase noise of the voltage controlled oscillator of the PPL circuit, and the presence of noise and hum sensitivity. It is not desirable because there will be significant jitter in the clock. In addition, circuits of this type are difficult to implement in integrated circuits.
    [22] In order to better understand the circuit shown in FIG. 4 from now on, an example of how the output signal having a frequency that is 6/13 of the input frequency Fi is generated will be discussed.
    [23] 2 shows a signal of an input frequency as a function of time. Individual periods of the input frequency Fi are also shown, which are represented by 0, 1, 2, ..., 11, 12, 0, .... Six different signals d1 to d6 are also shown. d1 is the same signal as the signal Fi but has a delay equal to 1/6 of the period of the signal Fi. Similarly, d2 is the same signal as signal Fi but with a delay of 2/6 of the period of signal Fi. Signals d3, d4, d5 and d6 are also delayed signals, which are the same as signal Fi, but are delayed by 3/6, 4/6, 5/6 and 6/6 of the period of the signal Fi, respectively. Since it is divided into 13/6, each of the 13 cycles of the aforementioned signal is shown, and a shift of 1/6 cycles occurs for each delay.
    [24] The output signal Fo completes exactly six periods within the time that the input signal Fi completes exactly thirteen periods, but the rising and falling edges of the continuous pulses of the signal Fo are independent of the two consecutive pulses of the signal Fo being considered. They must exist at the same time distance from each other. The number of periods of the signal Fo should be equal to six within a time when the signal Fi has 13 periods.
    [25] This is achieved as follows. The first pulse of the signal Fo, referred to as 0 in FIG. 2, has a rising edge that coincides with the rising edge of the first pulse of signal d1. The falling edge of pulse 0 of the output signal Fo coincides with the subsequent rising edge of the signal d1. In order to obtain a subsequent pulse, i.e., one rising edge of the signal Fo, it is switched over to the delayed signal d2. The rising edge of pulse 1 of the signal Fo coincides with the rising edge of the third pulse of the signal Fi, that is, the first pulse of the signal d2 that occurs after the second pulse. The falling edge of pulse 1 of signal Fo coincides with the fourth pulse of signal Fi, ie the rising edge of the pulse of the signal following pulse three. Similarly, the third pulse of the signal Fo, i.e. pulse 2, is achieved by a delay signal d3 which coincides with the fifth and sixth pulses of the signal Fi, i.e. pulses 4 and 5. respectively.
    [26] This continues even during the fourth, fifth and sixth pulses of the signal Fo, i.e., three, four and five pulses, which combine with the signals d4, d5 and d6. In the situation shown in FIG. 2, it should be noted that pulse number 10 of signal Fi does not follow the rising or falling edge of the pulse of signal Fo.
    [27] The above situation is implemented by a counter that counts the pulses of the signal Fi, where each pulse raises the counter score by 6, and the counter counts based on 13 (count modulo 13). A counter counting at 13 means that as soon as the counter's counter score rises above 13, 13 is subtracted from the next counter score. In Figure 2, the counter score of the counter is shown above the signal Fi. 3 is a table in which the counter scores of the counters are listed in column I. FIG. For example, counter score 0 in column I corresponds to 0 pulses of signal Fi, counter score 1 corresponds to pulse 11 of signal Fi, and counter score 2 corresponds to pulse 9 of signal Fi.
    [28] Column II shows the delayed signals d1 to d6 selected for each of the counter scores shown in column I. Column III is shown as the distance of the time at which the individual rising or falling edges of the signal Fo corresponding to the counter scores shown in column I occur, ie the period of the signal Fi. It is now evident that there is an invariant time lapse of 2 1/6 periods of the signal Fi between the constant, ie all two consecutive rising edges of the signal Fo. In other words, the duration of the signal Fo matches exactly 13/6 of the duration of the signal Fi, on average as well as from any one subsequent pulse.
    [29] Frequency division by 13/6 has been discussed above with reference to FIGS. 2 and 3 by way of example only. It is possible for one skilled in the art to create a similar relationship for any other ratio between Fo and Fi.
    [30] A circuit in which the foregoing can be implemented is shown in FIG. 4. 4 shows a signal source 1 which produces an output signal Fi and is connected to the counter 2 of the delay lock loop 4 and the clock input of the input 3. The output end of the counter 2 is connected to the input end of the decoder circuit 6 via the connection end 5. The output stage of the decoder circuit 6 includes a number of individual outputs connected to the same number of data input stages as the data flip-flops given by reference numerals 7 and 8. The clock input terminal of the data flip-flops 7 and 8 is connected to the output terminal of the signal generator 1. The delay lock loop 4 comprises a plurality of delay elements a, b, c, ..., R-2, R-1, R. The feedback of the last signal from the delay element R to the control circuit 9 ensures that the delay of the delay element remains in phase with the input signal Fi. Delay elements a, b, c, ... are connected to the clock input terminals of flip-flops 10, 11, 12, .... The data input terminals of the flip-flops 10, 11, 12, ... are connected to the first, second, third, ... data flip-flops 7, 8. The output end of the data flip-flops 10, 11, 12, ... is connected to the input end of the OR circuit 13. The signal Fo appears at the output of the OR circuit 13.
    [31] The operation of the circuit shown in FIG. 4 is as follows, the following technique being associated with the 13/6 divider discussed with reference to FIGS. 2 and 3.
    [32] The output signal Fi of the signal generator 1 is provided to the input stage 3 of the delay lock loop, in which case it comprises six delay elements a, b, c, R-2, R-1, R. . The counter 2 counts individual pulses of the signal Fi. After the first pulse, ie after 0 of the signal Fi, the signal appears on the connecting line 5 which represents 0. After the second pulse of signal Fi, a signal representing number 6 appears between lines 5. After the third pulse of signal Fi, the signal representing number 12 appears on line 5. After the fourth pulse 3, a signal 5 representing number 5 appears on the line 5. This continues with a subsequent pulse of signal Fi, where line 5 has a continuous signal indicating numbers 11, 4, 10, 3, 9, 2, 8, 1, 7 and then again zero.
    [33] From Table 3 of FIG. 3, when the signal representing the number 0 appears on the connection line 5, the rising edge of the signal Fi, which has been delayed once, will result in the rising edge of pulse 0 of the signal Fo.
    [34] Each of the delay elements (a, b, c, R-2, R-1, R) has the signal Fi being 1/6, 2/6, 3/6, 4/6, 5/6 and Delay each 6/6. This means that signal d1 (see FIG. 2) is at the output of the delay line, signal d2 is at the output of delay line b, signal d3 is at the output of delay line c, and signal d4 is at the output of delay line R-2. , Signal d5 is shown at the output of delay line R-1, and signal d6 is shown at the output of delay line R.
    [35] If one signal is not present at one particular output end of the decoder circuit, i.e. at one data input end of the multiple data flip-flops 7, the output of the decoder circuit 6 is due to the decoding of the signal on the connection line 5 0.
    [36] In the case of the invention, the counter score 0 is communicated by a signal on the connection line 5, the decoder circuit 6 being configured such that the first output 6a is one. The fact that the output 6a is 1 has the result that the output 7a becomes 1 on the subsequent pulse of the signal Fi at the clock input of the multiple data flip-flops 7. This one signal is brought into the data flip-flop 10 clocked by the output signal of the delay element with a delay of one sixth of one period of the input signal Fi, so that one signal on the line 7a is line 10a. Is sent to the output end of the data flip-flop (10).
    [37] In the same way, the counter 2 takes the counter score 6 on the subsequent pulse of the signal Fi. As a result, a signal is generated on the connection line 5 corresponding to the counter score 6, which is evident from Table 3 of FIG. 3, so that the connection line 6a is now switched to zero by the decoder 6, so that the line ( The input signal on 7a) will be zero when the subsequent clock pulse reaches a number of data flip-flops 7. Then, in the subsequent, once delayed pulse of delay line a provided to the clock input of data flip-flop 10, the output signal of data flip-flop 10 on line 10a is the signal on line 7a, It will be equal to zero. The first pulse of the signal Fo is formed accordingly. The rising edge of this first pulse has a delay of one sixth of one period of the signal Fi as compared to the rising edge of the number 0 pulse of the signal Fi. The duration of this first pulse between the rising edge and falling edge of this pulse number 0 of the signal Fo is also equal to the duration of the input signal Fi. The signal representing number 12 will appear on the connection line 5 at the output of the counter 2 upon the subsequent pulse 2 of the signal Fi. As is apparent from the table of FIG. 3, the decoder circuit 6 will ensure that the signal d2 delayed twice results in the generation of the second pulse 1 of the signal Fo. For this purpose, the decoder 6 makes the signal on the line 6b go high in response to the signal indicating number 12 on the connection line 5. In the same manner as described above with reference to the signal on connection line 6a that is high and subsequently low, the signal on line 6b becomes high and subsequently low again. The fact that the signal of the delay line b coming through the flip-flop 11 together with the signal on the output line 7b of the multiple flip-flops 7 is the second pulse of the signal Fo on the line 11a. Ensure that (1) is formed. The signal provided through the OR circuit 13 is the first pulse 0 of the signal Fo with a delay of 1/6 for the rising edge of pulse 0 and the 2 2 / of the signal Fi for the rising edge of pulse 0 of the signal Fi. Pulse 1 of the signal Fo with a rising edge with a delay of 6 cycles.
    [38] It is now apparent to those skilled in the art that pulses 2, 3, 4 and 5 of the signal Fo will be formed at the output of the OR circuit 13 in the same manner.
    [39] On the basis of the signals indicative from 0 to 12 on the connection line 5, a decoder circuit 6 is achieved in which the correction lines 6a, 6b, 6c, 6d or 6f become 1 and subsequently made 0 again. This is shown in the column of FIG. 3. Column IIb indicates whether the associated line has one signal or zero signal in response to the appearance of the number shown in column I on connection line 5.
    [40] It will now be apparent to those skilled in the art that fractional dividers having a ratio P / Q can be implemented for any two numbers P and Q. It is sufficient to configure the counter as well as the decoder circuit 6 based on the table shown in FIG. 3, which does not present any particular difficulty to those skilled in the art. All other elements such as flip-flops 7, 8, 10, 11, 12, ... and delay elements a, b, c, ... are known per se, used in a conventional manner. .
    [41] 5 shows a PLL frequency synthesizer in which the aforementioned fractional divider is used in a feedback loop. The circuit 5 shown in the figure includes a signal generator 20, a PLL circuit 21 and a divider 22. The output signal Fo of the PLL circuit 21 is connected to the input of the fractional divider 22, and then the output thereof is connected to the input of the PLL 21.
    [42] The frequency step size of the output signal of the PLL synthesizer in which the divider 22 dividing the output frequency Fo by an integer is equal to Fi. The frequency step size of the synthesizer with fractional division is shown in FIG. 5, where division N equals Q / P and equals Fi / P. Thus, the frequency resolution is P times larger. This means that the bandwidth of the loop can be chosen P times larger. The fact that the bandwidth can be chosen larger means that faster tuning times can be achieved, resulting in less noise (jitter), larger catchment area and higher resolution. The circuit can be implemented in a simple manner and is inexpensive.
    [43] 6 again shows a second application of a fractional N-splitter in a frequency synthesizer with a phase locked loop. The basic circuit diagram of the circuit is shown in FIG. 6 and known as a dithering synthesizer. Switching occurs between two dividends through feedback block 23. The output frequency Fo will then be the average of the input frequency Fi divided by the two dividends. For example, if the first dividend is 4 and the other dividend is 5, Fo switches between 4 times Fi and 5 times Fi, so that on average Fo equals between 4 and 5, for example 4.5 times Fi. I will do it. The input signal K on line 25 determines via the first-order sigma delta modulator 24 what the average frequency is. This case is known as standard technology, where N is an integer, the selection will be made by signal K on line 25 between division by N and division by N + 1. However, in the case of the present invention where division occurs by a circuit as described with reference to Figs. 2 to 4, one step of the dividend of the element 23 will not equal 1 but equal 1 / P. Thus, switching occurs between dividend N and dividend N + (1 / P). Thus, within the standard technique described above, the frequency resolution once equal to Fi will now be equal to (1 / P) * Fi.
    [44] A plurality of embodiments and variations of the circuit as described and shown above will now be apparent to those skilled in the art with reference to the above.
    权利要求:
    Claims (6)
    [1" claim-type="Currently amended] Rational number-The rational number is greater than 1 and can only be recorded with a denominator that is not equal to 1 when recorded as a vulgar fraction, i.e., of the first signal Fi divided into non-integers. An apparatus for generating a second signal Fo having a frequency equal to a frequency,
    A plurality connected in series to further delay the first signal Fi per delay element each time by a period equal to a time period of the first signal Fi divided by the denominator of the fraction of the rational number. Means for providing said first signal (Fi) to a first delay element (a) of delay elements (a, b, ..., R) of the counter, and a counter for counting pulses of said first signal (Fi) ( A combinatorial circuit comprising 2),
    The counting is done by increasing the denominator of the rational number and modulo it with the numerator of the rational number, resulting in a counter score,
    The combining circuit 6, 7, 8, 10, 11, 12, 13 comprises a decoder 6 which decodes the counter score based on an algorithm determined by the rational number-the decoded counter score Is represented as an output signal at one output end 6a, ..., 6e of the decoder circuit determined by the counter score and the algorithm each time-,
    The coupling circuits 6, 7, 8, 10, 11, 12, 13 are coupled with the output signal of the decoder circuit 6 to the output signal of the delay element determined by the algorithm to obtain the second signal Fo. Comprising means for coupling 7, 8, 10, 11, 12, 13
    Signal generator.
    [2" claim-type="Currently amended] The method of claim 1,
    The number of delay elements a, b, ... R is equal to the denominator of the rational number.
    Signal generator.
    [3" claim-type="Currently amended] The method according to claim 1 or 2,
    The number of outputs 6a, ..., 6e of the decoder circuit is equal to the denominator of the rational number.
    Signal generator.
    [4" claim-type="Currently amended] The method according to any one of claims 1 to 3,
    The delay elements a, b, ..., R are connected as delay phase loop circuits.
    Signal generator.
    [5" claim-type="Currently amended] In a phase locked loop circuit comprising a feedback loop,
    Apparatus according to any of claims 1 to 4 is included in the feedback loop.
    Phase locked loop circuit.
    [6" claim-type="Currently amended] A phase locked loop comprising a dithering possibility feedback loop,
    Apparatus according to any of claims 1 to 4 is included in the feedback loop.
    Phase locked loop circuit.
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    同族专利:
    公开号 | 公开日
    WO2001091298A3|2002-05-16|
    EP1290798A2|2003-03-12|
    WO2001091298A2|2001-11-29|
    JP2003534699A|2003-11-18|
    US6459753B2|2002-10-01|
    US20020006179A1|2002-01-17|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    法律状态:
    2000-05-19|Priority to EP00201777.0
    2000-05-19|Priority to EP00201777
    2001-04-24|Application filed by 롤페스 요하네스 게라투스 알베르투스, 코닌클리즈케 필립스 일렉트로닉스 엔.브이.
    2001-04-24|Priority to PCT/EP2001/004597
    2002-03-12|Publication of KR20020019541A
    优先权:
    申请号 | 申请日 | 专利标题
    EP00201777.0|2000-05-19|
    EP00201777|2000-05-19|
    PCT/EP2001/004597|WO2001091298A2|2000-05-19|2001-04-24|Fractional n-divider, and frequency synthesizer provided with a fractional n-divider|
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